Semiconductor Engineering

Power Grid Analysis

With increasing design size at each technology node, power grid analysis (PGA) has been stretching established software capacity and performance for some time. At 32/28nm, capacity and performance ...
EDN

Grid and resolution: Defining two critical terms in IC design

A recent trend confusing two quite different terms has had a huge negative impact on the yield, reliability, and manufacturability of DSM (deep-submicron) and subwavelength semiconductor designs. This ...
Design-Reuse

A design methodology using Power-Grid Prototyping to optimize Area Performance of SoCs

Set-Top-Box(STB) SoC designs are extremely complex with multi-million standard cells, higher core utilization of around 70-80 %, and multiple clock domains including high and low frequencies. An ...
Semiconductor Engineering

Power Grid Analysis

Power grids (PGs) have consumed an increasingly larger percentage of routing resources in recent process node generations, due to lower maximum current limits imposed by the foundry. It is not ...