Electronic Design

Graph-Based Test-Synthesis Tool Creates Verification Plans

The complexity of today's system-on-a-chip designs creates serious verification challenges in various respects. It's increasingly difficult to write an effective and comprehensive verification plan.
Semiconductor Engineering

LLM-based Agentic Framework Automating HW Security Threat Modeling And Test Plan Generation (U. of Florida)

A new technical paper titled “ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification” was published by researchers at University of Florida. “Current ...