PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...

For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it ...

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...

For many decades, progress in electronics has been driven by a gradual reduction in the size of silicon transistors (electronic switches). However, this scaling is becoming increasingly difficult and ...

A new automotive gate driver is redefining 48V mild-hybrid efficiency with configurable channels, built-in protection, and ...

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up.

Usually it takes a whole armada of engineers to design and fabricate a functional computer from scratch, so it is worth noting how this small research group has made a nanotube computer. The authors ...

Whereas the CPUs and similar ASICs of the 1970s had their transistors laid out manually, with the move from LSI to VLSI, it became necessary to optimize the process of laying out the transistors and ...

Guest author Ken Shirriff is a Silicon Valley-based computer enthusiast who enjoys reverse-engineering old chips and restoring classic equipment such as the Xerox Alto. Shirriff wrote the Arduino ...