Abstract: A dynamic comparator reset scheme based on the flying capacitor is proposed. The reset power used to charge the integration nodes of the comparator is nearly halved by exploiting the ...
Abstract: This article presents a 1.75-GS/s single-channel 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) that is based on loop-unrolled architecture with ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback