EDN

VLSI papers weigh 65 nm, new circuits

AUSTIN, Texas — While technologists look to 65-nanometer nodes, circuit designers by and large are two generations back. So it's no surprise that as a string of 65-nm papers are delivered at the 2004 ...
Electronic Design

Super-Smart Power Technology Scales Down To Nanometer Design Rules

As suppliers adopt 0.35-μm and finer CMOS features, they seek system-level integration with on-chip power MOSFETs. With the thrust toward system-level integration, smart power devices continue to make ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...
ksn.com

2D Graphene Interconnects for CMOS and Integrated Circuits

It is the world’s best diffusion barrier that prevents oxidation and metal migration in circuits. My fusion process is the only process in the world that can use 2D Graphene for circuit interconnects ...
EDN

VLSI conference papers weigh 65-nm, new circuits

AUSTIN, Texas — While technologists look to 65-nanometer nodes, circuit designers by and large are two generations back. So it's no surprise that as a string of 65-nm papers are delivered at the 2004 ...